Silicon Labs /EFR32MG21A020F512IM32 /RAC_S /SEQCTRL

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Interpret as SEQCTRL

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (WRAP)COMPACT 0 (NEVER)COMPINVALMODE 0 (X0)STIMERDEBUGRUN 0 (X0)CPUHALTREQEN 0 (X0)SEQHALTUPONCPUHALTEN

COMPACT=WRAP, SEQHALTUPONCPUHALTEN=X0, CPUHALTREQEN=X0, STIMERDEBUGRUN=X0, COMPINVALMODE=NEVER

Description

No Description

Fields

COMPACT

STIMER Compare Action

0 (WRAP): STIMER wraps when reaching STIMERCOMP

1 (CONTINUE): STIMER continues when reaching STIMERCOMP

COMPINVALMODE

STIMER Comp Invalid Mode

0 (NEVER): STIMERCOMP is always valid

1 (STATECHANGE): STIMERCOMP is invalidated when the RSM changes state

2 (COMPEVENT): STIMERCOMP is invalidated when an STIMER compare event occurs

3 (STATECOMP): STIMERCOMP is invalidated both when the RSM changes state and when a compare event occurs

STIMERDEBUGRUN

STIMER Debug Run

0 (X0): STIMER is not running when the Sequencer is halted.

1 (X1): STIMER is running when the Sequencer is halted.

CPUHALTREQEN

CPU Halt Request Enable

0 (X0): Main CPU is not halted when the Sequencer is halted.

1 (X1): Main CPU is halted when the Sequencer is halted.

SEQHALTUPONCPUHALTEN

Sequencer Halt Upon CPU Halt Enable

0 (X0): Sequencer is not halted when the main CPU is halted.

1 (X1): Sequencer is halted when the main CPU is halted.

Links

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